參數(shù)資料
型號(hào)： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁(yè)數(shù)： 3/59頁(yè)
文件大小： 4654K
代理商： KM416RD4C
Page 4
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
Table 3 : Pin Description
Signal
I/O
Type
# Pins
edge
# Pins
center
Description
SIO1,SIO0
I/O
CMOS
2
2
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
CMD
I
CMOS
1
1
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
SCK
I
CMOS
1
1
Serial clock input. Clock source used for reading from and writing
to the control registers
V
DD
14
6
Supply voltage for the RDRAM core and interface logic.
V
DDa
2
1
Supply voltage for the RDRAM analog circuitry.
V
CMOS
2
2
Supply voltage for CMOS input/output pins.
GND
19
9
Ground reference for RDRAM core and interface.
GNDa
2
1
Ground reference for RDRAM analog circuitry.
DQA8..DQA0
I/O
RSL
9
9
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAMs with a x16 organization.
CFM
I
RSL
1
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
CFMN
I
RSL
1
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
V
REF
1
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSL
1
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
CTM
I
RSL
1
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
I
RSL
3
3
Row access control. Three pins containing control and address
information for row accesses.
RQ4..RQ0 or
COL4..COL0
I
RSL
5
5
Column access control. Five pins containing control and address
information for column accesses.
DQB8..
DQB0
I/O
RSL
9
9
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQB8 is not used by
RDRAMs with a x16 organization.
Total pin count per package
74
54
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