參數(shù)資料
型號: KM416S1020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 16Bit x 2 Banks Synchronous DRAM(512K x 16位 x 2組同步動態(tài)RAM)
中文描述: 為512k × 16 × 2銀行同步DRAM(為512k × 16位× 2組同步動態(tài)RAM)的
文件頁數(shù): 2/42頁
文件大?。?/td> 582K
代理商: KM416S1020C
KM416S1020C
CMOS SDRAM
- 3 -
Rev. 0.4 (Apr. 1998)
The KM416S1020C is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS latency ( 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
512K x 16Bit x 2 Banks Synchronous DRAM
ORDERING INFORMATION
Part No.
Max Freq.
143MHz
125MHz
100MHz
100MHz
100MHz
Interface
Package
KM416S1020CT-G/F7
KM416S1020CT-G/F8
KM416S1020CT-G/FH
KM416S1020CT-G/FL
KM416S1020CT-G/F10
LVTTL
50
TSOP(II)
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 16
512K x 16
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
Timing Register
相關(guān)PDF資料
PDF描述
KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interfacer(512K x 16位 x 2組同步動態(tài)RAM(帶SSTL接口))
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