參數(shù)資料
型號: KM416S1020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 16Bit x 2 Banks Synchronous DRAM(512K x 16位 x 2組同步動態(tài)RAM)
中文描述: 為512k × 16 × 2銀行同步DRAM(為512k × 16位× 2組同步動態(tài)RAM)的
文件頁數(shù): 37/42頁
文件大?。?/td> 582K
代理商: KM416S1020C
TIMING DIAGRAM - I
CMOS SDRAM
ELECTRONICS
REV. 4 Nov. '97
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page
HIGH
Row Active
(A-Bank)
: Don't care
*Note :
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is same as the case of
Both cases are illustrated above timing diagram. See the label 0. 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
RAS interrupt.
*Note 2
Precharge
(A-Bank)
Burst Stop
Read
(A-Bank)
Read
(A-Bank)
1
2
1
2
BA
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
QAa0
QAa1
QAa2
QAa3
QAa4
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
RAa
CAa
CAb
RAa
相關(guān)PDF資料
PDF描述
KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interfacer(512K x 16位 x 2組同步動態(tài)RAM(帶SSTL接口))
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KM416S4021B 2M x 16Bit x 2 Banks Synchronous DRAM(2M x 16位 x2組同步動態(tài)RAM)
KM416S4030B 1M x 16Bitx 4 Banks Synchronous DRAM(1M x 16位 x4組同步動態(tài)RAM)
KM416S4031B 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface(1M x 16位 x4組同步動態(tài)RAM(帶SSTL接口))
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