參數(shù)資料
型號(hào)： KM416S1020C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512K x 16Bit x 2 Banks Synchronous DRAM(512K x 16位 x 2組同步動(dòng)態(tài)RAM)
中文描述： 為512k × 16 × 2銀行同步DRAM（為512k × 16位× 2組同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 9/42頁
文件大?。?/td> 582K
代理商： KM416S1020C
KM416S1020C
CMOS SDRAM
- 10
Rev. 0.4 (Apr. 1998)
SIMPLIFIED TRUTH TABLE
1. OP Code : Operand code
A
0
~ A
10
/AP, BA : Program keys. (@ MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at both banks precharge state.
4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A
10
/AP is "High" at row precharge, BA is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
(V=Valid, X=Don
′
t care, H=Logic high, L=Logic low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
A
10
/AP
A
9
~ A
0
Note
Register
Mode register set
H
X
L
L
L
L
X
OP code
1,2
Refresh
Auto refresh
H
H
L
L
L
H
X
X
3
Self
refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank active & row addr.
H
X
L
L
H
H
X
V
Row address
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
L
Column
address
(A
0
~ A
7
)
4
Auto precharge enable
H
4,5
Write &
column address
Auto precharge disable
H
X
L
H
L
L
X
V
L
Column
address
(A
0
~ A
7
)
4
Auto precharge enable
H
4,5
Burst stop
H
X
L
H
H
L
X
X
6
Precharge
Bank selection
H
X
L
L
H
L
X
V
L
X
Both banks
X
H
Clock suspend or
active power down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge power down mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
X
V
V
DQM
H
V
X
7
No operation command
H
X
H
X
X
X
X
X
L
H
H
H
RP
after the end of burst.
Notes :
相關(guān)PDF資料
PDF描述
KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interfacer(512K x 16位 x 2組同步動(dòng)態(tài)RAM（帶SSTL接口）)
KM416S4020B 2M x 16Bit x 2 Banks Synchronous DRAM(2M x 16位 x2組同步動(dòng)態(tài)RAM)
KM416S4021B 2M x 16Bit x 2 Banks Synchronous DRAM(2M x 16位 x2組同步動(dòng)態(tài)RAM)
KM416S4030B 1M x 16Bitx 4 Banks Synchronous DRAM(1M x 16位 x4組同步動(dòng)態(tài)RAM)
KM416S4031B 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface(1M x 16位 x4組同步動(dòng)態(tài)RAM（帶SSTL接口）)
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