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參數(shù)資料
| 型號： | KM416S1021CT-GS |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface |
| 中文描述： | 為512k × 16 × 2銀行同步DRAM接口的薩里衛(wèi)星技術(shù)有限公司 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 78K |
| 代理商： | KM416S1021CT-GS |
KM416S1021C
REV. 1. May '98
CMOS SDRAM
Preliminary
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-7
-S
-8
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
7
1000
-
1000
8
1000
ns
1
CAS latency=2
12
10
13
CLK to Valid
Output Delay
CAS latency=3
t
SAC
5.5
-
6
ns
1,2
CAS latency=2
7
6
8
Output data hold time
t
OH
2.5
2
2.5
ns
2
CLK high pulse width
t
CH
3
3.5
3
ns
3
CLK low pulse width
t
CL
3
3.5
3
ns
3
Input setup time
t
SS
2
2
2.5
ns
3
Input hold time
t
SH
1
1
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.5
-
6
ns
CAS latency=2
7
8
8
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
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| KM416S1120D | 512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416S1120D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/F10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/F6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/F7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/F8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
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