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參數(shù)資料
| 型號： | KM416S1120D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| 中文描述： | 為512k × 16位× 2銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 10/43頁 |
| 文件大?。?/td> | 1131K |
| 代理商： | KM416S1120D |
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KM416S1120D
CMOS SDRAM
- 10
Rev. 1.4 (Jun. 1999)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A
10
/AP
RFU
A
9
W.B.L
A
8
A
7
TM
A
6
A
5
A
4
A
3
BT
A
2
A
1
A
0
CAS Latency
Burst Length
A
8
0
0
1
1
A
7
0
1
0
1
Write Burst Length
Length
A
6
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
A
3
0
1
A
2
0
0
0
0
1
1
1
1
A
1
0
0
1
1
0
0
1
A
0
0
1
0
1
0
1
0
1
BT = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Test Mode
Type
Mode Register Set
Reserved
Reserved
Reserved
A
9
0
1
Burst
Single Bit
Latency
Reserved
-
2
3
Reserved
Reserved
Reserved
Reserved
CAS Latency
Burst Type
BT = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Length
Type
Sequential
Interleave
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note
: 1. If A
9
is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Full Page Length : x4 (1024), x8 (512), x16 (256)
BA
RFU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM416S16230A | 4M x 16Bit x 4 Banks Synchronous DRAM(4M x 16位 x4組同步動態(tài)RAM) |
| KM416S4030C | 1M x 16Bit x 4 Banks Synchronous DRAM |
| KM416S4030CT-F10 | 1M x 16Bit x 4 Banks Synchronous DRAM |
| KM416S4030CT-F7 | 1M x 16Bit x 4 Banks Synchronous DRAM |
| KM416S4030CT-F8 | 1M x 16Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416S1120DT-G/F10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/F6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/F7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/F8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S1120DT-G/FC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
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