參數(shù)資料
型號(hào)： KM416V4100B
廠(chǎng)商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4M x 16bit CMOS Dynamic RAM with Fast Page Mode(4M x 16位 CMOS動(dòng)態(tài)RAM(帶快速頁(yè)模式))
中文描述： 4米× 16位的快速頁(yè)面模式的CMOS動(dòng)態(tài)RAM（4米× 16位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶快速頁(yè)模式））
文件頁(yè)數(shù)： 1/35頁(yè)
文件大小： 753K
代理商： KM416V4100B
KM416V4000B,
KM416V4100B
CMOS DRAM
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-
thermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung
′
s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
Part Identification
- KM416V4000B/B-L(3.3V, 8K Ref.)
- KM416V4100B/B-L(3.3V, 4K Ref.)
Fast Page Mode operation
2CAS Byte/Word Read/Write operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
Fast parallel test mode capability
LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic TSOP(II) packages
+3.3V
±
0.3V power supply
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
4M x 16bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
Refresh Cycles
Part
NO.
Refresh
cycle
Refresh time
Normal
L-ver
KM416V4000B*
KM416V4100B
8K
4K
64ms
128ms
Performance Range
Speed
-45
-5
-6
t
RAC
45ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
80ns
90ns
110ns
t
PC
31ns
35ns
40ns
Active Power Dissipation
Speed
-45
-5
-6
8K
360
324
288
4K
468
432
396
Unit : mW
Control
Clocks
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Memory Array
4,194,304 x 16
Cells
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
S
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ
8
to
DQ15
OE
*
Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
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