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參數(shù)資料
| 型號(hào)： | KM416V4100B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 16bit CMOS Dynamic RAM with Fast Page Mode(4M x 16位 CMOS動(dòng)態(tài)RAM(帶快速頁模式)) |
| 中文描述： | 4米× 16位的快速頁面模式的CMOS動(dòng)態(tài)RAM（4米× 16位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶快速頁模式）） |
| 文件頁數(shù)： | 9/35頁 |
| 文件大?。?/td> | 753K |
| 代理商： | KM416V4100B |
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KM416V4000B,
KM416V4100B
CMOS DRAM
t
ASC
,
t
CAH
are referenced to the earlier CAS falling edge.
t
CP
is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
t
CWD
is referenced to the later CAS falling edge at word read-modify-write cycle.
t
CWL
is specified from W falling edge to the earlier CAS rising edge.
t
CSR
is referenced to the earlier CAS falling edge before RAS transition low.
t
CHR
is referenced to the later CAS rising edge after RAS transition low.
t
DS
is specified for the earlier CAS falling edge and
t
DH
is specified by the later CAS falling edge.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
t
CSR
t
CHR
RAS
LCAS
UCAS
t
DS
t
DH
LCAS
UCAS
DQ0 ~ DQ15
Din
21.
20.
19.
15.
14.
13.
18.
17.
16.
22.
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