參數(shù)資料
型號: KM44V4004C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 4Bit CMOS Dynamic RAM with Extended Data Out(4M x 4位 CMOS 動態(tài)RAM(帶擴展數(shù)據(jù)輸出))
中文描述: 4米× 4位的擴展數(shù)據(jù)輸出的CMOS動態(tài)RAM(4米× 4位的CMOS動態(tài)隨機存儲器(帶擴展數(shù)據(jù)輸出))
文件頁數(shù): 1/21頁
文件大?。?/td> 366K
代理商: KM44V4004C
KM44C4004C, KM44C4104C
KM44V4004C, KM44V4104C
CMOS DRAM
This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this
family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version.
This 4Mx4 EDO DRAM family is fabricated using Samsung
s advanced CMOS process to realize high band-width, low power consump-
tion and high reliability. It may be used as main memory unit for high level computer, microcomputer and personal computer.
Part Identification
- KM44C4004C/C-L (5V, 4K Ref.)
- KM44C4104C/C-L (5V, 2K Ref.)
- KM44V4004C/C-L (3.3V, 4K Ref.)
- KM44V4104C/C-L (3.3V, 2K Ref.)
Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
Fast parallel test mode capability
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
Single +5V
±
10% power supply (5V product)
Single +3.3V
±
0.3V power supply (3.3V product)
Control
Clocks
RAS
CAS
W
Vcc
Vss
DQ0
to
DQ3
A0-A11
(A0 - A10)
*1
A0 - A9
(A0 - A10)
*1
Memory Array
4,194,304 x4
Cells
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
4M x 4Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
V
CC
Refresh
cycle
Refresh period
Normal
L-ver
C4004C
V4004C
C4104C
V4104C
5V
3.3V
5V
3.3V
4K
64ms
128ms
2K
32ms
Performance Range
t
RAC
-5
50ns
-6
60ns
Speed
t
CAC
15ns
17ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
Remark
5V/3.3V
5V/3.3V
Active Power Dissipation
Speed
3.3V
5V
4K
324
288
2K
396
360
4K
495
440
2K
605
550
-5
-6
Unit : mW
S
Data out
Buffer
Data in
Buffer
OE
Note)
*1
: 2K Refresh
Col. Address Buffer
Row Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
Column Decoder
Row Decoder
VBB Generator
相關(guān)PDF資料
PDF描述
KM44V4104C 4M x 4Bit CMOS Dynamic RAM with Extended Data Out(4M x 4位 CMOS 動態(tài)RAM(帶擴展數(shù)據(jù)輸出))
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