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參數(shù)資料
| 型號： | KM48S32230A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8M x 8Bit x 4 Banks Synchronous DRAM(8M x 8位 x 4組同步動態(tài)RAM) |
| 中文描述： | 8米× 8位× 4銀行同步DRAM（8米× 8位× 4組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 62K |
| 代理商： | KM48S32230A |
KM48S32230A
CMOS SDRAM
REV. 0 May '98
Preliminary
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
°
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
Input logic high voltage
V
IH
2.0
3.0
V
DD
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
IL
-5
-
5
uA
3
Output leakage current
I
OL
-5
-
5
uA
4
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
+0.3V, all other pins are not under test = 0V.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD.
Notes :
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°
C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Clock
C
CLK
2.5
4
pF
Input capacitance (A0 ~ A12, BA0 ~BA1)
C
IN1
2.5
5
pF
Input capacitance
(CKE, CS, RAS, CAS, WE & DQM)
C
IN2
2.5
5
pF
Data input/output capacitance (DQ
0
~DQ
7
)
C
OUT
4
6.5
pF
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