參數(shù)資料
型號(hào)： KM48S8030B
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 8Bit x 4 Banks Synchronous DRAM(2M x 8位 x 4組同步動(dòng)態(tài)RAM)
中文描述： 200萬× 8位× 4銀行同步DRAM（2米× 8位× 4組同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 14/43頁
文件大?。?/td> 625K
代理商： KM48S8030B
CMOS SDRAM
DEVICE OPERATIONS - III
ELECTRONICS
REV. 3 Feb. '98
DEVICE OPERATIONS
ADDRESS INPUTS (A0 ~ A11)
: In case x 4
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 12 address input pins (A
0
~ A
11
).
The 12 bit row addresses are latched along with RAS and BA
0
~
BA
1
during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA
0
~ BA
1
dur-
ing read or write command.
: In case x 8
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A
0
~ A
11
).
The 12 bit row addresses are latched along with RAS and BA
0
~
BA
1
during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA
0
~ BA
1
during read or
write command.
: In case x 16
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 12 address input pins (A
0
~ A
11
).
The 12 bit row addresses are latched along with RAS and BA
0
~
BA
1
during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA
0
~ BA
1
during read or
write command.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin-
gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.
POWER-UP
Apply power and start clock, Attempt to maintain CKE= "H",
DQM= "H" and the other pins are NOP condition at the
inputs.
Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.
Issue precharge commands for both banks of the devices.
Issue 2 or more auto-refresh commands.
Issue a mode register set command to initialize the mode
register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
1.
2.
3.
4.
5.
CLOCK (CLK)
The clock input is used as the reference for all SDRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock.
The clock transitions must be monotonic between
V
IL
and V
IH
. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and I
CC
specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the-
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + t
SS
" before the high going edge
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.
BANK ADDRESSES (BA0 ~ BA1)
: In case x 4
This SDRAM is organized as four independent banks of
4,194,304 words x 4 bits memory arrays. The BA
0
~ BA
1
inputs
are latched at the time of assertion of RAS and CAS to select
the bank to be used for the operation. The bank addresses BA
0
~ BA
1
are latched at bank active, read, write, mode register set
and precharge operations.
: In case x 8
This SDRAM is organized as four independent banks of
2,097,152 words x 8 bits memory arrays. The BA
0
~ BA
1
inputs
are latched at the time of assertion of RAS and CAS to select
the bank to be used for the operation. The bank addresses BA
0
~ BA
1
are latched at bank active, read, write, mode register set
and precharge operations.
: In case x 16
This SDRAM is organized as four independent banks of
1,048,576 words x 16 bits memory arrays. The BA
0
~ BA
1
inputs
are latched at the time of assertion of RAS and CAS to select
the bank to be used for the operation. The bank addresses BA
0
~ BA
1
are latched at bank active, read, write, mode register set
and precharge operations.
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