參數(shù)資料
型號(hào): KM48S8030B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 8Bit x 4 Banks Synchronous DRAM(2M x 8位 x 4組同步動(dòng)態(tài)RAM)
中文描述: 200萬(wàn)× 8位× 4銀行同步DRAM(2米× 8位× 4組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 2/43頁(yè)
文件大小: 625K
代理商: KM48S8030B
KM48S8030B
CMOS SDRAM
REV. 6 June '98
The KM48S8030B is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2M x 8Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
Part No.
Max Freq.
125MHz
100MHz
100MHz
100MHz
Interface Package
KM48S8030BT-G/F8
KM48S8030BT-G/FH
KM48S8030BT-G/FL
KM48S8030BT-G/F10
LVTTL
54
TSOP(II)
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
2M x 8
2M x 8
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 8
2M x 8
Timing Register
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