參數(shù)資料
型號: KM6161000B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 64K x16 Bit Low Power CMOS Static RAM(64K x16位低功耗 CMOS 靜態(tài)RAM)
中文描述: 64K的x16位低功耗CMOS靜態(tài)RAM(64K的x16位低功耗的CMOS靜態(tài)RAM)的
文件頁數(shù): 8/9頁
文件大?。?/td> 135K
代理商: KM6161000B
KM6161000B Family
CMOS SRAM
Revision 2.0
February 1998
8
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS going low to end of write.
3.
t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end or write to the address change.
t
WR
applied in case a write ends as CS or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
DATA RETENTION WAVE FORM
CS controlled
V
CC
4.5V
2.2V
V
DR
CS
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
t
AS(3)
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KM6161002A 64K x 16 Bit High-Speed CMOS Static RAM(64K x 16位高速CMOS 靜態(tài)RAM)
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KM6161002B 64K x 16 Bit High-Speed CMOS Static RAM(64K x 16位高速CMOS 靜態(tài)RAM)
KM6161002BI 64K x 16 Bit High-Speed CMOS Static RAM(64K x 16位高速CMOS 靜態(tài)RAM)
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