參數(shù)資料
型號: KM6164002B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256K x 16 Bit High-Speed CMOS Static RAM(256Kx16位低功耗CMOS 靜態(tài) RAM)
中文描述: 256K × 16位高速CMOS靜態(tài)RAM(256Kx16位低功耗的CMOS靜態(tài)RAM)的
文件頁數(shù): 4/9頁
文件大?。?/td> 150K
代理商: KM6164002B
KM6164002B, KM6164002BI
CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 2.1
June 1998
- 4 -
PRELIMINARY
TEST CONDITIONS
NOTE: The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
°
C, V
CC
=5.0V
±
10%, unless otherwise noted.)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
D
OUT
5pF*
480
255
+5.0V
* Including Scope and Jig Capacitance
READ CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM6164002B-10
KM6164002B-12
KM6164002B-15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
10
-
12
-
15
-
ns
Address Access Time
t
AA
-
10
-
12
-
15
ns
Chip Select to Output
t
CO
-
10
-
12
-
15
ns
Output Enable to Valid Output
t
OE
-
5
-
6
-
7
ns
UB, LB Access Time
t
BA
-
5
-
6
-
7
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
5
0
6
0
7
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
0
7
ns
UB, LB Disable to High-Z Output
t
BHZ
0
5
0
6
0
7
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
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