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參數資料
| 型號： | KM6164002E |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CMOS SRAM |
| 中文描述： | CMOS SRAM的 |
| 文件頁數： | 4/9頁 |
| 文件大小： | 167K |
| 代理商： | KM6164002E |
KM6164002, KM6164002E, KM6164002I
CMOS SRAM
PRELIMINARY
Rev 2.0
June -1997
- 6 -
TIMING WAVE FORM OF READ CYCLE(2)
(WE=V
IH
)
CS
OE
Data Out
Data Valid
ADD
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to device.
5. Transition is measured
±
200
§
from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
OH
or V
OL
Levels.
UB, LB
UB, LB
TIMING WAVE FORM OF WRITE CYCLE(1)
(OE=Clock)
OE
CS
Data In
WE
High-Z
ADD
Data Out
Data Valid
High-Z(8)
t
RC
t
AA
t
CO
t
BLZ(4,5)
t
OE
t
BA
t
OLZ
t
LZ(4,5)
t
HZ(3,4,5)
t
BHZ(3,4,5)
t
OHZ
t
OH
t
WC
t
AW
t
WP(2)
t
BW
t
CW(3)
t
AS(4)
t
OHZ(6)
t
DW
t
DH
t
WR(5)
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相關代理商/技術參數 |
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|---|---|
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