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參數(shù)資料
| 型號(hào)： | KM616S4110C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx16 Bit Low Power and Low Voltage CMOS Static RAM(256K x 16位低功耗低電壓CMOS 靜態(tài)RAM) |
| 中文描述： | 256Kx16位低功耗和低電壓的CMOS靜態(tài)RAM（256K × 16位低功耗低電壓的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大小： | 166K |
| 代理商： | KM616S4110C |
KM616S4110C Family
CMOS SRAM
Preliminary
Revision 0.01
August 1998
8
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS
1
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
1
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS
1
going low to end of write.
3.
t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end or write to the address change.
t
WR
applied in case a write ends as CS
1
or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
2.3V
2.0V
V
DR
CS, LB/UB
GND
Data Retention Mode
CS1
≥
V
CC
- 0.2V
t
SDR
t
RDR
t
AS(3)
CS
1
CS
2
CS
2
controlled
V
CC
2.3V
CS
2
0.4V
GND
V
DR
Data Retention Mode
t
SDR
t
RDR
CS
2
≤
0.2V
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