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參數(shù)資料
| 型號(hào)： | KM616U4110C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx16 Bit Low Power and Low Voltage CMOS Static RAM(256K x 16位低功耗低電壓CMOS 靜態(tài) RAM) |
| 中文描述： | 256Kx16位低功耗和低電壓的CMOS靜態(tài)RAM（256K × 16位低功耗低電壓的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | KM616U4110C |
KM616U4110C Family
CMOS SRAM
Preliminary
Revision 0.01
August 1998
5
C
L
1
)
1.Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
≥
Vcc-0.2V,CS
2
≥
Vcc-0.2V(CS
1
controlled) or CS
2
≥
Vcc-0.2V(CS
2
controlled)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
≥
Vcc-0.2V
1)
Vcc=2.5V, CS
1
≥
Vcc-0.2V
1)
2.0
-
3.3
V
Data retention current
I
DR
-
0.5
20
μ
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
AC CHARACTERISTICS
(Vcc=2.7~3.3V, T
A
=-40 to 85
°
C)
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
100ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
100
-
ns
Address access time
t
AA
-
70
-
85
-
100
ns
Chip select to output
t
CO
-
70
-
85
-
100
ns
Output enable to valid output
t
OE
-
35
-
40
-
50
ns
LB, UB valid to data output
t
BA
-
70
-
85
-
100
ns
Chip select to low-Z output
t
LZ
10
-
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
5
-
ns
LB, UB enable to low-Z output
t
BLZ
10
-
10
-
10
-
ns
Output hold from address change
t
OH
10
-
10
-
15
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
25
0
30
ns
OE disable to high-Z output
t
OHZ
0
25
0
25
0
30
ns
UB, LB disable to high-Z output
t
BHZ
0
25
0
25
0
30
ns
Write
Write cycle time
t
WC
70
-
85
-
100
-
ns
Chip select to end of write
t
CW
60
-
70
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
-
80
-
ns
Write pulse width
t
WP
55
-
60
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
25
0
30
ns
Data to write time overlap
t
DW
30
-
35
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
5
-
ns
LB, UB valid to end of write
t
BW
60
-
70
-
80
-
ns
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