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參數(shù)資料
| 型號： | KM616V1002B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(64K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| 中文描述： | 64K的× 16位高速CMOS靜態(tài)RAM（3.3V的工作）（64K的× 16位高速的CMOS靜態(tài)隨機存儲器（3.3V的工作）） |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 158K |
| 代理商： | KM616V1002B |
KM616V1002B/BL, KM616V1002BI/BLI
CMOS SRAM
PRELIMINARY
PPreliminary
Rev 2.1
- 5 -
August 1998
WRITE CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM616V1002B/BL-8
KM616V1002B/BL-10
KM616V1002B/BL-12
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
8
-
10
-
12
-
ns
Chip Select to End of Write
t
CW
6
-
7
-
8
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
6
-
7
-
8
-
ns
Write Pulse Width(OE High)
t
WP
6
-
7
-
8
-
ns
Write Pulse Width(OE Low)
t
WP1
8
-
10
-
12
-
ns
UB, LB Valid to End of Write
t
BW
6
-
7
-
8
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
4
0
5
0
6
ns
Data to Write Time Overlap
t
DW
4
-
5
-
6
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB, LB=V
IL
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Valid Data
High-Z
t
RC
CS
Address
UB, LB
OE
Data out
t
HZ(3,4,5)
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
BHZ(3,4,5)
t
BLZ(4,5)
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
相關PDF資料 |
PDF描述 |
|---|---|
| KM616V1002BI | 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(64K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| KM616V1002C | 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(64K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| KM616V1002CI | 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(64K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| KM616V4002B | 256K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(256K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| KM616V4002BI | 256K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(256K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KM616V1002BT-10 | 制造商:SEC 功能描述: |
| KM616V4002BT15 | 制造商:SAMSUNG 功能描述:* |
| KM616V4002BT-15 | 制造商:Samsung Electro-Mechanics 功能描述:Static RAM, 256Kx16, 44 Pin, Plastic, TSOP 制造商:Seco Electronic Device 功能描述:Static RAM, 256Kx16, 44 Pin, Plastic, TSOP |
| KM6-19-20PN | 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk |
| KM6-19-20PN-FO | 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk |
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