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參數(shù)資料
| 型號(hào)： | KM616V1002C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(64K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| 中文描述： | 64K的× 16位高速CMOS靜態(tài)RAM（3.3V的工作）（64K的× 16位高速的CMOS靜態(tài)隨機(jī)存儲(chǔ)器（3.3V的工作）） |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 160K |
| 代理商： | KM616V1002C |
KM616V1002C/CL, KM616V1002CI/CLI
CMOS SRAM
PRELIMINARY
PRELIMINARY
Revision 0.0
Aug. 1998
- 5 -
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB, LB=V
IL
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Valid Data
High-Z
t
RC
CS
Address
UB, LB
OE
Data out
t
HZ(3,4,5)
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
BHZ(3,4,5)
t
BLZ(4,5)
WRITE CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM616V1002C/CL-12
KM616V1002C/CL-15
KM616V1002C/CL-20
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
12
-
15
-
20
-
ns
Chip Select to End of Write
t
CW
8
-
9
-
10
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
8
-
9
-
10
-
ns
Write Pulse Width(OE High)
t
WP
8
-
9
-
10
-
ns
Write Pulse Width(OE Low)
t
WP1
12
-
15
-
20
-
ns
UB, LB Valid to End of Write
t
BW
8
-
9
-
10
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
6
0
7
0
9
ns
Data to Write Time Overlap
t
DW
6
-
7
-
8
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
t
PU
t
PD
50%
50%
V
CC
Current
I
CC
I
SB
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