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參數(shù)資料
| 型號： | KM616V4002BI |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)(256K x 16 位高速CMOS 靜態(tài) RAM(3.3V 工作)) |
| 中文描述： | 256K × 16位高速CMOS靜態(tài)RAM（3.3V的工作）（256K × 16位高速的CMOS靜態(tài)隨機存儲器（3.3V的工作）） |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 157K |
| 代理商： | KM616V4002BI |
KM616V4002B/BL, KM616V4002BI/BLI
CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 2.1
June 1998
- 6 -
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE Clock)
Address
CS
UB, LB
WE
Data in
Data out
t
WC
t
CW(3)
t
BW
t
WP(2)
t
AS(4)
t
DH
t
DW
t
OHZ(6)
High-Z
High-Z
Valid Data
OE
t
AW
t
WR(5)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low fixed)
Address
CS
UB, LB
WE
Data in
Data out
t
WC
t
CW(3)
t
BW
t
WP1(2)
t
DH
t
DW
t
WR(5)
t
AS(4)
t
OW
t
WHZ(6)
(10)
(9)
High-Z
Valid Data
t
AW
High-Z
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM616V4002BT15 | 制造商:SAMSUNG 功能描述:* |
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