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參數(shù)資料
| 型號(hào)： | KM62U256CLG-10L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx8 bit Low Power AND Low Vcc CMOS Static RAM |
| 中文描述： | 32Kx8位低功耗和低成本嚇的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 90K |
| 代理商： | KM62U256CLG-10L |
ELECTRONICS
KM62V256C, KM62U256C Family
CMOS SRAM
Revision 04
April 1996
-
8
-
TIMING WAVEFORM OF WRITE CYCLE
(/WE Controlled)
Address
/WE
Data in
/CS
t
WC
t
WP(1)
t
WHZ
t
WR(4)
t
DH
t
AS
t
CW(2)
t
OW
Data out
t
AW
t
DW
Data Valid
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE
(/CS Controlled)
t
WC
t
CW(2)
t
WR(4)
t
AW
t
WP(1)
Address
/CS
/WE
Data in
Data out
t
DW
Data Valid
t
AS
High - Z
High - Z
DH
t
Notes (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of a low /CS and low /WE. A write begins at the latest transition among
/CS going low and /WE going low : A write end at the earliest transition among /CS going high and /WE going
high, tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE
going high.
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| KM62U256CLG-8L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Kx8 bit Low Power AND Low Vcc CMOS Static RAM |
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