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參數(shù)資料
| 型號： | KMM374F224BJ1 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 72 DRAM DIMM(2Mx72 動態(tài) RAM模塊) |
| 中文描述： | 200萬× 72的DRAM內存（2Mx72動態(tài)內存模塊） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 388K |
| 代理商： | KMM374F224BJ1 |
DRAM MODULE
KMM374F224BJ1
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are
reference levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL loads and 100pF,
Voh=2.0V and Vol=0.8V.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
,
t
RWD,
t
CWD
and
t
AWD
are non-restrictive operating
parameter. They are inclueded in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early
write cycle and the data out pin will remain high impedance
for the duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min) and
t
AWD
≥
t
AWD
(min), then the cycle is a read-write
cycle and the data output will contain the data read from the
selected address. If neither of the above contitions are satis-
fied, the condition of the data out is indeterminated.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
t
ASC
≥
6ns
If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit cond-
tion of the output is achieved by RAS high going.
t
ASC
,
t
CAH
are referenced to the earlier CAS falling edge.
t
CP
is specified from the last CAS rising edge in the previous
cycle to the first CAS falling edge in the next cycle.
t
CWD
is referenced to the later CAS falling edge at word read-
modify-write cycle.
t
CWL
is specified from W falling edge to the earlier CAS rising
edge.
t
CSR
is referenced to earlier CAS falling low before RAS tran-
sition low.
t
CHR
is referenced to later CAS rising high after RAS transi-
tion low.
t
DS,
t
DH
is independently specified for lower byte DIN(0~7),
upper byte DIN(8~15).
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