參數(shù)資料
型號(hào): L6740L
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對(duì)AMD SVID和PVID)處理器
文件頁(yè)數(shù): 37/44頁(yè)
文件大?。?/td> 657K
代理商: L6740L
L6740L
System control loop compensation
37/44
9
System control loop compensation
The device embeds two separate and independent control loops for CORE and NB section.
The control loop for NB section is a simple Voltage-Mode control loop with (optional) voltage
positioning featured when DROOP pin is shorted with FB. The control loop for the CORE
section also features a Current-Sharing loop to equalize the current carried by each of the
configured phases.
The CORE control system can be modeled with an equivalent Single-Phase converter
whose only difference is the equivalent inductor L/N (where each phase has an L inductor
and N is the number of the configured phases). See
Figure 16
.
Figure 16.
Equivalent control loop for NB and CORE sections.
This means that the same analysis can be used for both the sections with the only exception
of the different equivalent inductor value (L=L
NB
for NB Section and L=L
CORE
/N for the
CORE section) and the current reading gain (R
dsON
/R
ISEN
for NB Section and DCR/R
G
for
the CORE Section).
The Control Loop gain results (obtained opening the loop after the COMP pin):
Where:
R
LL
is the equivalent output resistance determined by the droop function;
Z
P
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)
and the applied load R
O
;
Z
F
(s) is the compensation network impedance;
Z
L
(s) is the equivalent inductor impedance;
A(s) is the error amplifier gain;
is the PWM transfer function.
PWM
10
V
OSC
The Control Loop gain for each section is designed in order to obtain a high DC gain to
minimize static error and to cross the 0dB axes with a constant -20dB/Dec. slope with the
desired crossover frequency
ω
T
. Neglecting the effect of Z
F
(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance
ω
LC
) and the zero (
ω
ESR
) is fixed by ESR and the Droop resistance.
Ref
N
NB_COMP
N
N
R
F_NB
C
F-NB
R
FB_NB
N
PWM
L
NB
ESR_NB
C
O_NB
R
O
d V
NB_COMP
V
OUT_NB
Z
F
(s)
Z
FB
(s)
I
D
VID_NB
V
N
Ref
F
COMP
V
F
R
F
C
F
R
FB
D
PWM
L
CORE
/N
ESR
C
O
R
O
d V
COMP
V
OUT
Z
F
(s)
Z
FB
(s)
I
D
VID_CORE
V
C
G
LOOP
s
( )
PWM Z
s
( )
s
A s
R
Z
s
( )
+
(
)
Z
P
s
( )
Z
L
s
( )
+
[
]
--------------
1
A s
-----------
+
R
FB
+
-------------------------------------------------------------------------------------------------------------------
=
------
------------------
=
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