參數(shù)資料
型號: L6740LTR
廠商: 意法半導體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對AMD SVID和PVID)處理器
文件頁數(shù): 11/44頁
文件大?。?/td> 657K
代理商: L6740LTR
L6740L
Pins description and connection diagrams
11/44
31
N
NB_VSEN
NB output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the
positive side of the NB load to perform remote sensing. See
Section 9
for proper layout of this connection.
32
NB_DROOP
A current proportional to the total current read by the NB section is
sourced through this pin according to the Current Reading Gain
(R
ISEN
). Short to NB_FB to implement Droop Function or connect to
SGND through a resistor and filter with 1nF capacitor to implement NB
LOAD Indicator. If not used, short to SGND.
33
NB_FB
NB error amplifier inverting input.
Connect with a resistor R
FB_NB
to NB_VSEN and with an R
F_NB
- C
F_NB
to NB_COMP. Offset current programmed by NB_OS is sunk through
this pin.
34
NB_COMP
Error amplifier output.
Connect with an R
F_NB
- C
F_NB
to NB_FB. The NB Section or the device
cannot be disabled by grounding this pin.
35,
36
S
VID0, VID1
Voltage IDentification Pins.
Internally pulled-low by 10
μ
A, they are used to program the output
voltage. VID1 is monitored on the EN pin rising-edge to define the
operative mode of the controller (SVI or PVI). When in SVI Mode, VID0
is ignored. See
Section 5
for details.
37
PWROK
System-wide Power Good Input (SVI Mode).
Internally pulled-low by 10
μ
A. When low, the device will decode the two
SVI bits (SVC, SVD) to determine the
Pre-PWROK Metal VID
(default
condition when pin is floating).
When high, the device will actively run the SVI protocol.
Pre-PWROK Metal VID
are latched after EN is asserted and re-used in
case of PWROK de-assertion. Latch is reset by VCC or EN cycle.
38
EN
VR Enable. Internally pulled-up to 3.3V by 10
μ
A.
Pull-low to disable the device. When set free, the device immediately
checks for the VID1 status to determine the SVI / PVI protocol to be
adopted and configures itself accordingly. See
Section 5
for details.
39
S
SVC / VID3
Voltage IDentification Pin - SVI Clock Pin.
Internally pulled-low by 10
μ
A, it is used to program the output voltage.
When in SVI-Mode, it is considered as Serial-VID-Data (Input / Open
Drain Output). See
Section 5
for details.
40
SVD / VID2
Voltage IDentification Pins - SVI Data Pin.
Internally pulled-low by 10
μ
A, it is used to program the output voltage.
When in SVI-Mode, it is considered as Serial-VID-Data (Input / Open
Drain Output). See
Section 5
for details.
41
PWRGOOD
VCORE and NB Power Good.
It is an open-drain output set free after SS as long as both the voltage
planes are within specifications. Pull-up to 3.3V (typ) or lower, if not
used it can be left floating.
When in PVI Mode, it monitors the CORE Section only.
Table 2.
Pin description (continued)
Pin#
Name
Function
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