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參數(shù)資料
| 型號： | L6740LTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Hybrid controller (4+1) for AMD SVID and PVID processors |
| 中文描述： | 混合控制器（4 1對AMD SVID和PVID）處理器 |
| 文件頁數(shù)： | 18/44頁 |
| 文件大?。?/td> | 657K |
| 代理商： | L6740LTR |
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Hybrid CPU support and CPU_TYPE detection
L6740L
18/44
5.3
SVI - serial interface
SVI is a two wire, Clock and Data, bus that connects a single master (CPU) to one slave
(L6740L). The master initiates and terminates SVI transactions and drives the clock, SVC,
and the data, SVD, during a transaction. The slave receives the SVI transactions and acts
accordingly. SVI wire protocol is based on fast-mode I
2
C.
SVI interface also considers two additional signal needed to manage the system start-up.
These signals are EN and PWROK. The device return a PWRGOOD signal if the output
voltages are in regulation.
5.4
SVI start-up
Once the SVI mode has been detected on the EN rising-edge, L6740L checks for the status
of the two serial VID pins, SVC and SVD, and stores this value as the
Pre-PWROK Metal
VID
. The controller initiate a soft-start phase regulating both CORE and NB voltage planes
to the voltage level prescribed by the
Pre-PWROK Metal VID
. See
Table 7
for details about
Pre-PWROK Metal VID
codifications. The stored
Pre-PWROK Metal VID
value are re-used
in any case of PWROK de-assertion.
After bringing the output rails into regulation, the controller asserts the PWRGOOD signal
and waits for PWROK to be asserted. Until PWROK is asserted, the Controller regulates to
the
Pre-PWROK Metal VID
ignoring any commands coming from the SVI interface.
After PWROK is asserted, the processor has initialized the serial VID interface and L6740L
waits for commands from the CPU to move the voltage planes from the
Pre-PWROK Metal
VID
values to the operative VID values. As long as PWROK remains asserted, the controller
will react to any command issued through the SVI interface according to SVI Protocol.
See
Section 6.10
for details about Soft-Start.
Table 7.
V_FIX mode and MetalVID
5.4.1
Set VID command
The
Set VID Command
is defined as the command sequence that the CPU issues on the
SVI bus to modify the voltage level of the CORE Section and/or the NB Section.
During a
Set VID Command
, the processor sends the start (START) sequence followed by
the address of the Section which the
Set VID Command
applies. The processor then sends
the write (WRITE) bit. After the write bit, the Voltage Regulator (VR) sends the acknowledge
(ACK) bit. The processor then sends the VID bits code during the
data phase
. The VR
sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop
(STOP) sequence. After the VR has detected the stop, it performs an On-the-Fly VID
SVC
SVD
Output voltage [V]
Pre-PWROK Metal VID
V_FIX Mode
0
0
1.1V
1.4V
0
1
1.0V
1.2V
1
0
0.9V
1.0V
1
1
0.8V
0.8V
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