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參數(shù)資料
| 型號： | LCZM |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-/14-/12-Bit VOUT DACs in 3mm 】 3mm DFN |
| 中文描述： | 16/14/12 VOUT電源數(shù)模轉換器采用3mm DFN封裝】3毫米 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 317K |
| 代理商： | LCZM |
LTC2641/LTC2642
11
26412f
OPERATION
The digital-to-analog transfer function at the V
OUT
pin
is:
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and V
REF
is between 2.0V and
V
DD
(see Tables 1a, 1b and 1c).
The LTC2642 includes matched resistors that are tied to
an external amplifier to provide bipolar output swing (Fig-
ure 2). The bipolar transfer function at the RFB pin is:
V
k
N
2
V
OUT IDEAL
(
REF
)
=
(see Tables 2a, 2b and 2c).
V
V
k
N
OUT BIPOLAR IDEAL
_
REF
(
)
–
–
1
=
2
1
Serial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire SPI/QSPI/MICROWIRE compatible interface. The
chip select input (
C
S) controls and frames the loading
of serial data from the data input (DIN). Following a
C
S
high-to-low transition, the data on DIN is loaded, MSB
first, into the shift register on each rising edge of the serial
clock input (SCLK). After 16 data bits have been loaded
into the serial input register, a low-to-high transition on
C
S
transfers the data to the 16-bit DAC latch, updating the DAC
output (see Figures 1a, 1b, 1c). While
C
S remains high,
the serial input shift register is disabled. If there are less
than 16 low-to-high transitions on SCLK while
C
S remains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on SCLK while
C
S remains low, only the last 16 data bits
loaded from DIN will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB
remains in the same (left-justified) position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LSB, to make up the required 16 data
bits (Figure 1b). Similarly, for the 12-bit family members
(LTC2641-12/LTC2642-12) four “don’t-care” bits must
follow the LSB (Figure 1c).
D15
MSB
1
CS
SCLK
DIN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D14
D13
D12
D11
D10
D9
D8
DATA (16 BITS)
D7
D6
D5
D4
D3
D2
D1
D0
LSB
DAC
UPDATED
26412 F01a
D13
MSB
1
CS
SCLK
DIN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D12
D11
D10
D9
D8
D7
D6
DATA (14 BITS + 2 DON’T-CARE BITS)
D5
D4
D3
D2
D1
D0
LSB
X
X
DAC
UPDATED
26412 F01b
MSB
1
CS
SCLK
DIN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D11
D10
D9
D8
D7
D6
DATA (12 BITS + 4 DON’T-CARE BITS)
Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12)
D5
D4
D3
D2
D1
D0
LSB
X
X
X
X
DAC
UPDATED
26412 F01c
Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14)
Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16)
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