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參數(shù)資料
| 型號(hào)： | LXP730 |
| 廠商： | Intel Corp. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 20/70頁 |
| 文件大?。?/td> | 531K |
| 代理商： | LXP730 |
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LXP730
—
Multi-Rate DSL Framer
20
Datasheet
The MDSL interface provides loopback of TDATA, bypassing the external RDATA. Loopback is
activated by setting the DSL_LB bit in the OVRHD_CFG register (24h). This routes the 64 kbps
channels and MDSL Overhead (MOH) from the MX section to the DX section. When using an
external loopback configuration, such as FELB in the SK70725, it is necessary to switch the DX
de-scrambling polynomial to the MX polynomial. The descrambling polynomial is inverted by
setting the REMOTE_LB bit of the FIFO_MISC register (17h). The BITCLK and QUATCLK
control the transfer of data from the MX to the DX section.
2.9
All Digital PLL (ADPLL)
The LXP730 ADPLL is necessary for clock recovery and to control output jitter and wander
produced in the DSL environment.
The ADPLL uses MCLK to drive the NCO circuitry, while the reference frequency comes from the
received DSL frame rate that has a nominal 6 ms period.
2.9.1
ADPLL Performance: The Selection of K
loop
The performance of the ADPLL is user programmable via a register. As shown in
Table 3
, the 5-bit
value, K
loop
, in PLLCTL3 register controls the lock time and the bandwidth of the ADPLL. The
lock time is the amount of time required for the ADPLL to acquire and synchronize to the input
MDSL signal. The bandwidth of the ADPLL determines the jitter rejection characteristics of the
ADPLL. The bandwidth and lock time are inversely related: BW = 3/T
lock
.
Kloop is a 5 bit control field found in register PLLCTL3 (address 1D hex, 29 dec). The register bits
are used to select a constant (Kloop_Value) that controls the loop bandwidth.
The Bandwidth of the loop filter is determined from the selected Kloop_Value and the frequency of
MCLK. Loop bandwidth (BW) is calculated as follows:
Table 3. K
loop
Values
Register Bits
Kloop_Value
00000
PLL freeze
00001
2
0
00010
2
-1
00011
2
-2
00100
2
-3
...
...
11111
2
-30
BW (3db) = Kloop_Value
×
MCLK
×
3.89e-5 Hz
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