參數(shù)資料
型號： M38C32E6MXXXFS
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 9/62頁
文件大?。?/td> 881K
代理商： M38C32E6MXXXFS
9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Fig. 7 Memory map of special function register (SFR)
ROM correct high-order address register 1
(Note)
ROM correct low-order address register 1
(Note)
ROM correct high-order address register 2
(Note)
ROM correct low-order address register 2
(Note)
ROM correct high-order address register 3
(Note)
ROM correct low-order address register 3
(Note)
ROM correct high-order address register 4
(Note)
ROM correct low-order address register 4
(Note)
Port P8 output selection register (P8SEL)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Serial I/O register (SIO)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Interrupt control register 2 (ICON2)
Timer 6 PWM register (T6PWM)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
φ
output control register (CKOUT)
Timer A register (low) (TAL)
Timer A register (high) (TAH)
Compare register (low) (CONAL)
Compare register (high) (CONAH)
Timer A mode register (TAM)
Timer A control register (TACON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Timer 6 (T6)
PULL register A (PULLA)
PULL register B (PULLB)
Segment output enable register (SEG)
LCD mode register (LM)
A-D control register (ADCON)
A-D conversion register (low) (ADL)
A-D conversion register (high) (ADH)
0F0A
16
0F0B
16
0F0C
16
0F0D
16
0F0E
16
0F0F
16
0F10
16
0F11
16
ROM correct enable register 1
(Note)
ROM correct high-order address register 5
(Note)
ROM correct low-order address register 5
(Note)
ROM correct high-order address register 6
(Note)
ROM correct low-order address register 6
(Note)
ROM correct high-order address register 7
(Note)
ROM correct low-order address register 7
(Note)
ROM correct high-order address register 8
(Note)
ROM correct low-order address register 8
(Note)
0F01
16
0F02
16
0F03
16
0F04
16
0F05
16
0F06
16
0F07
16
0F08
16
0F09
16
Note:
This register is valid only in mask ROM version.
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