參數(shù)資料
型號： M38C32EBAXXXFS
廠商： Mitsubishi Electric Corporation
英文描述： Quad 2.7-V High-Slew-Rate Rail-to-Rail Output Operational Amplifier 14-PDIP -40 to 125
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 23/62頁
文件大?。?/td> 881K
代理商： M38C32EBAXXXFS
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Fig. 21 Timing chart of timer A PWM, IGBT output modes
I
Notes on Timer A
(1) Write order to timer A
In the timer and pulse output modes, write to the timer A register
(low-order) first and to the timer A register (high-order) next. Do not
write to only one side.
In the IGBT and PWM modes, write to the registers as follows:
the compare register (high- and low-order)
the timer A register (low-order)
the timer A register (high-order).
It is possible to use whichever order to write to the compare register
(high- and low-order). However, write both the compare register and
the timer A register at the same time.
(2) Read order to timer A
In all modes, read to the timer A register (high-order) first and to the
timer A register (low-order) next. Read order to the compare regis-
ter is not specified.
If reading to the timer A register during write operation or writing to
it during read operation, normal operation will not be performed.
(3) Write to timer A
When writing a value to the timer A address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer A
address, the value is set into the timer and the timer latch at the
same time, because they are written at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, an ex-
pected value may be set in the high-order counter.
Do not switch the timer count source during timer count operation.
Stop the timer count before switching it. Additionally, when perform-
ing write to the latch and the timer at the same time, the timer count
value may change large.
(4) Set of timer A mode register
Set the write control bit to “1” (write to the latch only) when setting the
IGBT and PWM modes.
Output waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer A register (high-
order).
(5) Output control function of timer A
When using the output control function (INT
1
and INT
2
) in the IGBT
mode, set the levels of INT
1
and INT
2
to “H” in the falling edge active
or to “L” in the rising edge active before switching to the IGBT mode.
t
s
Timer A count
source
Timer A
PWM mode
IGBT output mode
(n-m+1)
ts
m
ts
(n+1)
ts
Note:
PWM waveform (duty : (n-m+1)/(n+1) and period : (n+1)
ts) is output.
n : setting value of Timer A
m : setting value of compare register
ts : period of Timer A count source
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