參數(shù)資料
型號: M38C33M4MXXXFP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 10/62頁
文件大?。?/td> 881K
代理商: M38C33M4MXXXFP
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
I/O PORTS
[Direction Registers (ports P2, P4, P5
0
, P5
2
–P5
7
,
and P6–P8)]
The I/O ports P2, P4, P5
0
, P5
2
–P5
7
, and P6–P8 have direction reg-
isters which determine the input/output direction of each individual
pin. Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
[Direction Registers (ports P0 and P1)]
Ports P0 and P1 have direction registers which determine the input/
output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output.
When “0” is written to the bit 0 of a direction register, that port be-
comes an input port. When “1” is written to that port, that port be-
comes an output port. Bits 1 to 7 of ports P0 and P1 direction regis-
ters are not used.
Pull-up/Pull-down Control
By setting the PULL register A (address 0016
16
) or the PULL register
B (address 0017
16
), ports except for ports P3 and P5
1
can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with a
program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Port P8 Output Selection
Ports P8
0
to P8
7
can be switched to N-channel open-drain output by
setting “1” to the port P8 output selection register.
Fig. 8 Structure of PULL register A and PULL register B
Pin
P0
0
/SEG
8
P0
7
/SEG
15
P1
0
/SEG
16
P1
7
/SEG
23
P2
0
/SEG
0
P2
7
/SEG
7
P3
0
/SEG
24
P3
7
/SEG
31
Name
Port P0
Port P1
Port P2
Port P3
Input/Output
Input/Output,
port unit
Input/Output,
port unit
Input/Output,
individual bits
Output,
individual bits
I/O format
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
CMOS 3-state output
CMOS 3-state output
Non-port function
LCD segment output
LCD segment output
LCD segment output
LCD segment output
Related SFRs
PULL register A
Segment output enable reg-
ister
PULL register A
Segment output enable reg-
ister
PULL register A
Segment output enable reg-
ister
Segment output enable reg-
ister
Ref. No.
(1)
(2)
Table 4 List of I/O port function (1)
Fig. 9 Structure of port P8 output selection register
P0
0
–P0
7
pull-down
P1
0
–P1
7
pull-down
P2
0
–P2
7
pull-down
Not used
P7
0
, P7
1
pull-up
P8
0
–P8
7
pull-up
PULL register A
(PULLA : address 0016
16
)
b7
b0
P4
0
–P4
3
pull-up
P4
4
–P4
7
pull-up
P5
0
, P5
2
, P5
3
pull-up
P5
4
–P5
7
pull-up
P6
0
, P6
3
pull-up
P6
4
–P6
7
pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
PULL register B
(PULLB : address 0017
16
)
b7
b0
Note :
The contents of PULL register A and PULL register B
do not affect ports programmed as the output ports.
Not used (return “0” when read)
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Port P8 output selection register
(P8SEL : address 0018
16
)
b7
b0
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