參數(shù)資料
型號(hào)： M38C35EBMXXXFS
廠商： Mitsubishi Electric Corporation
英文描述： 11-uA/Channel, 160kHz, RR-Out Op Amp 5-SOT-23 -40 to 125
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 27/62頁(yè)
文件大小： 881K
代理商： M38C35EBMXXXFS
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
LCD DRIVE CONTROL CIRCUIT
The 38C3 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output enable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for a LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
Fig. 27 Structure of LCD related registers
segment output enable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio
1
2
3
4
Maximum number of display pixels
32 dots
or 8 segment LCD 4 digits
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
Segment output enable bit 0
0 : I/O ports P2
0
–P2
3
1 : Segment output SEG
0
–SEG
3
Segment output enable bit 1
0 : I/O ports P2
4
–P2
7
1 : Segment output SEG
4
–SEG
7
Segment output enable bit 2
0 : I/O ports P0
0
–P0
3
1 : Segment output SEG
8
–SEG
11
Segment output enable bit 3
0 : I/O ports P0
4
–P0
7
1 : Segment output SEG
12
–SEG
15
Segment output enable bit 4
0 : I/O ports P1
0
–P1
3
1 : Segment output SEG
16
–SEG
19
Segment output enable bit 5
0 : I/O ports P1
4
–P1
7
1 : Segment output SEG
20
–SEG
23
Segment output enable bit 6
0 : Output ports P3
0
–P3
3
1 : Segment output SEG
24
–SEG
27
Segment output enable bit 7
0 : Output ports P3
4
–P3
7
1 : Segment output SEG
28
–SEG
31
Segment output enable register
(SEG : address 0038
16
)
b7
b0
LCD mode register
(LM : address 0039
16
)
Duty ratio selection bits
0 0 : 1 (use COM
0
)
0 1 : 2 (use COM
0
,COM
1
)
1 0 : 3 (use COM
0
–COM
2
)
1 1 : 4 (use COM
0
–COM
3
)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit.)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit
(Note)
0 : f(X
CIN
)/32
1 : f(X
IN
)/8192 (f(X
CIN
)/8192 in low-speed mode)
Note :
LCDCK is a clock for a LCD timing controller.
b7
b0
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