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參數(shù)資料
| 型號： | M38C36M2AXXXFS |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | Codec |
| 英文描述： | Programmable PCM Codec With Microphone Amps & Speaker Driver 80-BGA MICROSTAR JUNIOR -40 to 85 |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 37/62頁 |
| 文件大?。?/td> | 881K |
| 代理商： | M38C36M2AXXXFS |
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37
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
X
IN
X
OUT
External oscillation circuit
V
CC
V
SS
open
X
CIN
X
COUT
C
CIN
C
COUT
Rf
Rd
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf
Rd
CLOCK GENERATING CIRCUIT
The 38C3 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between X
IN
and
X
OUT
(X
CIN
and X
COUT
). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No external re-
sistor is needed between X
IN
and X
OUT
since a feedback resistor
exists on-chip. However, an external feedback resistor is needed be-
tween X
CIN
and X
COUT
.
Immediately after power on, only the X
IN
oscillation circuit starts os-
cillating, and X
CIN
and X
COUT
pins function as I/O ports.
Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of X
IN
divided by 8. After
reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of X
IN
divided by 2.
(3) Low-speed mode
The internal system clock is the frequency of X
CIN
divided by 2.
I
Notes on clock generating circuit
If you switch the mode between middle/high-speed and low-speed,
stabilize both X
IN
and X
CIN
oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(X
IN
) > 3f(X
CIN
).
Oscillation control
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and X
IN
and X
CIN
oscillators stop. Timer 1 is set to “FF
16
”
and timer 2 is set to “01
16
.”
Either X
IN
divided by 16 or X
CIN
divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before execut-
ing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 2 underflows. This allows time for the clock circuit oscilla-
tion to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of X
IN
and X
CIN
are the same as the state
before executing the WIT instruction. The internal system clock re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
Fig. 40 Ceramic resonator circuit
Fig. 41 External clock input circuit
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