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參數資料
| 型號： | M38C37M5MXXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數： | 15/62頁 |
| 文件大小： | 881K |
| 代理商： | M38C37M5MXXXFP |
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15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
INTERRUPTS
Interrupts occur by sixteen sources: six external, nine internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1.The processing being executed is stopped.
2.The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3.The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
I
Notes on Interrupts
When the active edge of an external interrupt (INT
0
– INT
2
, CNTR
0
or CNTR
1
) is set or an vector interrupt source where several interrupt
source is assigned to the same vector address is switched, the cor-
responding interrupt request bit may also be set. Therefore, take fol-
lowing sequence:
(1) Disable the interrupt.
(2) Change the active edge in interrupt edge selection register.
(3) Clear the set interrupt request bit to “0.”
(4) Enable the interrupt.
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