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參數(shù)資料
| 型號： | AD606JR-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC AMP LOG LP 1.2MA 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 對數(shù) |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 電流 - 輸入偏壓： | 4µA |
| 電流 - 電源： | 13mA |
| 電流 - 輸出 / 通道： | 1.2mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
AD606
REV. B
–6–
Offset-Control Loop
The offset-control loop nulls the input offset voltage, and sets
up the bias voltages at the input pins INHI and INLO. A full
understanding of this offset-control loop is useful, particularly
when using larger input coupling capacitors and an external
filter capacitor to lower the minimum acceptable operating
frequency. The loop’s primary purpose is to extend the lower
end of the dynamic range in the case where the offset voltage of
the first stage should be high enough to cause later stages to
prematurely enter limiting, because of the high dc gain (about
8000) of the main amplifier system. For example, an offset
voltage of only 20
V would become 160 mV at the output of
the last stage in the main amplifier (before the final limiter sec-
tion), driving the last stage well into limiting. In the absence of
noise, this limiting would simply result in the logarithmic output
ceasing to become any lower below a certain signal level at the
input. The offset would also degrade the logarithmic conform-
ance in this region. In practice, the finite noise of the first stage
also plays a role in this regard, even if the dc offset were zero.
Figure 3 shows a representation of this loop, reduced to essen-
tials. The figure closely corresponds to the internal circuitry,
and correctly shows the input resistance. Thus, the forward gain
of the main amplifier section is 7
× 11.15 dB, but the loop gain
is lowered because of the attenuation in the network formed by
RB1 and RB2 and the input resistance RA. The connection
polarity is such as to result in negative feedback, which reduces
the input offset voltage by the dc loop gain, here about 50 dB,
that is, by a factor of about 316. We use a differential representa-
tion, because later we will examine the consequences to the
power-up response time in the event that the ac coupling capaci-
tors CC1 and CC2 do not exactly match. Note that these capaci-
tors, as well as forming a high-pass filter to the signal in the
forward path, also introduce a pole in the feedback path.
TO FINAL
LIMITER
STAGE
+1
RB1
30k
RB2
30k
RA
2.5k
CF2
30pF
CF1
30pF
0V
RF2
360k
RF1
360k
FIL2
FIL1
CZ
RZ
CC1
CC2
78dB
Figure 3. Offset Control Loop
Internal resistors RF1 and RF2 in conjunction with grounded
capacitors CF1 and CF2 form a low-pass filter at 15 kHz. This
frequency can optionally be lowered by the addition of an exter-
nal capacitor CZ, and in some cases a series resistor RZ. This, in
conjunction with the low-pass section formed at the input cou-
pling, results in a two-pole high-pass response, falling of at
40 dB/decade below the corner frequency. The damping factor
of this filter depends on the ratio CZ/CC (when CZ>>CF) and
also on the value of RZ.
The inclusion of this control loop has no effect on the high frequency
response of the AD606. Nor does it have any effect on the low fre-
quency response when the input amplitude is substantially above the
input offset voltage.
The loop’s effect is felt only at the lower end of the dynamic
range, that is, from about 80 dBm to –70 dBm, and when the
signal frequency is near the lower edge of the passband. Thus,
the small signal results which are obtained using the suggested
model are not indicative of the ac response at moderate to high
signal levels. Figure 4 shows the response of this model for the
default case (using CC = 100 pF and CZ = 0) and with CZ =
150 pF. In general, a maximally flat ac response occurs when CZ
is roughly twice CC (making due allowance for the internal
30 pF capacitors). Thus, for audio applications, one can use
CC = 2.7 F and CZ = 4.7 F to achieve a high-pass corner
(–3 dB) at 25 Hz.
90
70
–20
100k
100M
10M
1M
10k
80
60
40
50
20
30
10
–10
0
INPUT FREQUENCY – Hz
RELATIVE
OUTPUT
–
dB
CZ = 150pF
CZ = 0pF
Figure 4. Frequency Response of Offset Control Loop for
CZ = 0 pF and CZ = 150 pF (CC = 100 pF)
However, the maximally flat ac response is not optimal in two
special cases. First, where the RF input level is rapidly pulsed,
the fast edges will cause the loop filter to ring. Second, ringing
can also occur when using the power-up feature, and the ac
coupling capacitors do not exactly match in value. We will ex-
amine the latter case in a moment. Ringing in a linear amplifier
is annoying, but in a log amp, with its much enhanced sensitiv-
ity to near zero signals, it can be very disruptive.
To optimize the low level accuracy, that is, achieve a highly
damped pulse response in this filter, it is recommended to in-
clude a resistor RZ in series with an increased value of CZ. Some
experimentation may be necessary, but for operation in the
range 3 MHz to 70 MHz, values of CC = 100 pF, CZ = 1 nF
and RZ = 2 k are near optimal. For operation down to 100 kHz
use CC = 10 nF, CZ = 0.1 F and RZ = 13 k. Figure 5 shows
typical connections for the AD606 with these filter components
added.
INHI
COMM
PRUP
VPOS
FIL1
FIL2
LADJ
LMHI
INLO
COMM
ISUM
ILOG
BFIN
VLOG
OPCM
LMLO
AD606JN
RZ
CZ
Figure 5. Use of CZ and RZ for Offset Control Loop
Compensation
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