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參數(shù)資料
| 型號(hào)： | XC6SLX25T-4FGG484C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 24K 484FGGBGA |
| 產(chǎn)品變化通告： | Spartan-6 LXT -4 Discontinuation 10/Jan/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Spartan® 6 LXT |
| LAB/CLB數(shù)： | 1879 |
| 邏輯元件/單元數(shù)： | 24051 |
| RAM 位總計(jì)： | 958464 |
| 輸入/輸出數(shù)： | 250 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA |
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
8
Low-Power Gigabit Transceiver
Ultra-fast data transmission between ICs, over the backplane, or over longer distances is becoming increasingly popular and
important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity
issues at these high data rates.
All Spartan-6 LXT devices have 2–8 gigabit transceiver circuits. Each GTP transceiver is a combined transmitter and
receiver capable of operating at data rates up to 3.2 Gb/s. The transmitter and receiver are independent circuits that use
separate PLLs to multiply the reference frequency input by certain programmable numbers between 2 and 25, to become
the bit-serial data clock. Each GTP transceiver has a large number of user-definable features and parameters. All of these
can be defined during device configuration, and many can also be modified during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 8, 10, 16, or 20. The transmitter
output drives the PC board with a single-channel differential current-mode logic (CML) output signal.
TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from
the internal logic. The incoming parallel data is fed through a small FIFO and can optionally be modified with the 8B/10B
algorithm to guarantee a sufficient number of transitions. The bit-serial output signal drives two package pins with
complementary CML signals. This output signal pair has programmable signal swing as well as programmable pre-
emphasis to compensate for PC board losses and other interconnect characteristics.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit serial differential signal into a parallel
stream of words, each 8, 10, 16, or 20 bits wide. The receiver takes the incoming differential data stream, feeds it through a
programmable equalizer (to compensate for the PC board and other interconnect characteristics), and uses the FREF input
to initiate clock recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ)
encoding and optionally guarantees sufficient data transitions by using the 8B/10B encoding scheme. Parallel data is then
transferred into the FPGA logic using the RXUSRCLK clock. The serial-to-parallel conversion ratio can be 8, 10, 16, or 20.
Integrated Endpoint Block for PCI Express Designs
The PCI Express standard is a packet-based, point-to-point serial interface standard. The differential signal transmission
uses an embedded clock, which eliminates the clock-to-data skew problems of traditional wide parallel buses.
The PCI Express Base Specification 1.1 defines bit rate of 2.5 Gb/s per lane, per direction (transmit and receive). When
using 8B/10B encoding, this supports a data rate of 2.0 Gb/s per lane.
The Spartan-6 LXT devices include one integrated Endpoint block for PCI Express technology that is compliant with the PCI
Express Base Specification Revision 1.1. This block is highly configurable to system design requirements and operates as
a compliant single lane Endpoint. The integrated Endpoint block interfaces to the GTP transceivers for serialization/de-
serialization, and to block RAMs for data buffering. Combined, these elements implement the physical layer, data link layer,
and transaction layer of the protocol.
Xilinx provides a light-weight (<200 LUT), configurable, easy-to-use LogiCORE IP that ties the various building blocks (the
integrated Endpoint block for PCI Express technology, the GTP transceivers, block RAM, and clocking resources) into a
compliant Endpoint solution. The system designer has control over many configurable parameters: maximum payload size,
reference clock frequency, and base address register decoding and filtering.
More information and documentation on solutions for PCI Express designs can be found at:
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