MC68336/376
MOTOROLA
USER’S MANUAL
vii
(Continued)
Paragraph
Title
Page
TABLE OF CONTENTS
5.10.2
Data Direction Registers ................................................................. 5-64
5.10.3
Data Registers ................................................................................. 5-64
5.11
Factory Test ............................................................................................ 5-64
SECTION 6 STANDBY RAM MODULE
6.1
SRAM Register Block ................................................................................ 6-1
6.2
SRAM Array Address Mapping ................................................................. 6-1
6.3
SRAM Array Address Space Type ............................................................ 6-1
6.4
Normal Access .......................................................................................... 6-2
6.5
Standby and Low-Power Stop Operation .................................................. 6-2
6.6
Reset ......................................................................................................... 6-3
SECTION 7 MASKED ROM MODULE
7.1
MRM Register Block .................................................................................. 7-1
7.2
MRM Array Address Mapping ................................................................... 7-1
7.3
MRM Array Address Space Type .............................................................. 7-2
7.4
Normal Access .......................................................................................... 7-2
7.5
Low-Power Stop Mode Operation ............................................................. 7-3
7.6
ROM Signature .......................................................................................... 7-3
7.7
Reset ......................................................................................................... 7-3
SECTION 8 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
8.1
General ...................................................................................................... 8-1
8.2
QADC Address Map .................................................................................. 8-2
8.3
QADC Registers ........................................................................................ 8-2
8.4
QADC Pin Functions ................................................................................. 8-2
8.4.1
Port A Pin Functions .......................................................................... 8-3
8.4.1.1
Port A Analog Input Pins ........................................................... 8-4
8.4.1.2
Port A Digital Input/Output Pins ................................................ 8-4
8.4.2
Port B Pin Functions .......................................................................... 8-4
8.4.2.1
Port B Analog Input Pins ........................................................... 8-4
8.4.2.2
Port B Digital Input Pins ............................................................ 8-4
8.4.3
External Trigger Input Pins ................................................................ 8-5
8.4.4
Multiplexed Address Output Pins ...................................................... 8-5
8.4.5
Multiplexed Analog Input Pins ........................................................... 8-5
8.4.6
Voltage Reference Pins ..................................................................... 8-5
8.4.7
Dedicated Analog Supply Pins .......................................................... 8-6
8.4.8
External Digital Supply Pin ................................................................ 8-6
8.4.9
Digital Supply Pins ............................................................................ 8-6
336376UMBook Page vii Friday, November 15, 1996 2:09 PM