參數(shù)資料
型號： MC68HC705CJ4FB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 50/114頁
文件大?。?/td> 4047K
代理商： MC68HC705CJ4FB
GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
Rev. 2.1
8-3
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go high and transmission will be considered to be complete. The TXD pin also will
revert to being a general purpose input line.
When the TE control bit is cleared (and left clear), the transmit logic gives up
control of the port D pin in the following controlled manner. If no data is being
shifted out and the transmitter is in an idle state (TC = 1), then when TE is cleared
the port D pin immediately reverts to being a general purpose input line. If a
transmission was still in progress (TC = 0), the character in the transmit shift
register will continue to be shifted out normally including any stop bit. When this
character is finished, the TXD pin reverts to being a general purpose input line
regardless of whether any data is pending in the TDR (TDRE is a don’t care). In
order to avoid accidentally cutting off the transmitter before the last character in a
message, the software should always wait for TDRE to go high following the last
write to TDR before clearing TE.
Another transmit-related SCI function is the send break function. This function is
used to abort transmissions by sending a minimum of 10 (11 if nine data bit format
is specified) bit times of space (logic zeros). The break function is invoked by
writing a one to the SBK bit in the SCCR2 register. If SBK is set while a
transmission is in progress, then the character in the transmit shift register will be
finished normally (including stop bit) before the break function begins. The logic
zero state on the TXD line will be a minimum of 10 (11) bit times but will continue
indefinitely as long as the SBK bit remains set. To guarantee the minimum break
time, SBK should just be toggled quickly to a one and back to zero. After a break
period, at least one bit time of mark (logic one) will be transmitted to guarantee
recognition of a subsequent start bit.
8.3 Receive Operation
The receive logic in the SCI is divided into two major sections. The first section is
a front end that synchronizes to the asynchronous receive data and evaluates the
logic sense of each bit in the serial stream. The second section controls the
functional operation and the interface to the CPU.
8.3.1 Receiver Front End
Due to the asynchronous nature of this serial communication system, the receiver
has a significant section of logic dedicated to gaining bit time synchronization with
the incoming data and evaluating the logic sense of each bit time in the serial data
stream. An understanding of this receiver front end logic is required before the
functional operation of the remaining receive logic can be explained. This receiver
front end logic uses a clock that is 16 times the baud rate frequency as a sampling
clock (The sampling clock is called the RT clock in the following discussions.). In
the remainder of this discussion, one RT is understood to be 1/16 of a bit time.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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