參數(shù)資料
型號(hào): MC705JP7CPE
廠商: Freescale Semiconductor
文件頁數(shù): 129/164頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
標(biāo)準(zhǔn)包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 6KB(6K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
Port C (28-Pin Versions Only)
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
67
7.4 Port C (28-Pin Versions Only)
Port C is an 8-bit, general-purpose, bidirectional I/O port with these features:
Individual programmable pulldown devices
High current sinking capability on all port C pins, with a maximum total for port C
High current sourcing capability on all port C pins, with a maximum total for port C
7.4.1 Port C Data Register
The port C data register (PORTC) contains a bit for each of the port C pins. When a port C pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port C pin is programmed to be an input, reading the port C data register returns the logic state of the pin.
PC7–PC0 — Port C Data Bits
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in the port C data direction register (DDRC). Reset has no effect on port C data.
7.4.2 Data Direction Register C
The contents of the port C data direction register (DDRC) determine whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the associated port C pin. A
DDRC bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRC bit
disables the output buffer for the associated port C pin. A reset initializes all DDRC bits to logic 0s,
configuring all port C pins as inputs.
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears the DDRC7–DDRC0 bits.
1 = Corresponding port C pin configured as output and pulldown device disabled
0 = Corresponding port C pin configured as input
Address:
$0002
Bit 7
654321
Bit 0
Read:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Write:
Reset:
Unaffected by reset
Figure 7-13. Port C Data Register (PORTC)
Address:
$0006
Bit 7
654321
Bit 0
Read:
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Write:
Reset:
00000000
Figure 7-14. Data Direction Register C (DDRC)
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