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參數(shù)資料
| 型號： | ML6401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit 20MSa/s Video A/D Converter(8位20MSa/s視頻A/D轉(zhuǎn)換器) |
| 中文描述： | 8位20MSa / s的視頻A / D轉(zhuǎn)換器（8位20MSa /秒視頻的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 233K |
| 代理商： | ML6401 |
4
ML6401
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Characteristics
Maximum CLK Input Frequency
20
25
MHz
Clock Duty Cycle
CLK = 13.5MHz
40
60
%
t
PWH
CLK - 20MHz
25
ns
t
PWL
CLK - 20MHz
25
ns
Analog To Digital Converter Inputs — CLK
Low Level Input Voltage
V
IL
0
0.8
V
High Level Input Voltage
V
IH
2.4
VDD
D
V
Low Level Input Current
V
IL
= 0.1V
–5
+5
μA
High Level Input Current
V
IH
= VDD
D
– 0.1V
–5
+5
μA
Input Capacitance
4.0
pF
TIMING — DIGITAL OUTPUTS (C
L
= 15pF, I
OL
= 2mA, R
L
= 2k
W
, f
CLK
= 20MHz)
Sampling Delay
t
DS
5
ns
Output Hold Time
t
HO
4
12
10
ns
Output Delay Time
t
DO
5
18
30
ns
3-State Delay Time
Output Enable
10
25
ns
3-State Delay Time
Output Disable
10
20
ns
ANALOG TO DIGITAL CONVERTER OUTPUTS — DIGITAL
Low Level Output Voltage
I
OL
= 2mA
0
0.6
V
High Level Output Voltage
I
OH
= 2mA
2.4
VCC
O
V
Output Current in 3-State Mode
–20
+20
μA
SUPPLIES
Analog Supply Current
Static
26
34
mA
Digital Supply Current
f
CLK
= 20MHz
10
15
mA
Output Supply Current
f
CLK
= 20MHz, C
L
= 0pF
4
10
mA
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
(V
IN
+) – (V
IN
–)
CLK
D0 TO D7
SAMPLE
OUT
N
N+1
N+2
N+3
N+4
N–3
N–2
N–1
N
N+1
t
DS
t
PWH
t
PWL
t
HO
t
DO
Figure 1. Timing Diagram
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