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參數(shù)資料
| 型號(hào)： | MPC750ARX333TH |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | CERAMIC, BGA-255 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 507K |
| 代理商： | MPC750ARX333TH |
The PowerPC 750 and PowerPC 740 microprocessors are low-power 32-bit implementations of the
PowerPC Reduced Instruction Set Computer (RISC) architecture. The PowerPC 750 and the PowerPC 740
microprocessors differ only in that the PowerPC 750 features a dedicated L2 cache interface with on-chip L2
tags. Both are software-compatible and bus-compatible with the PowerPC 603e and MPC7400 micro-
processors, and the PowerPC 740 is pin-compatible as well. PowerPC 750/740 microprocessors are fully
JTAG-compliant.
Superscalar Microprocessor
The PowerPC 750/740 microprocessors are superscalar, capable
of issuing three instructions per clock cycle into six independent
execution units:
I
Two integer units
I
Load/store unit
I
Floating-point unit
I
System register unit
I
Branch processing unit
The ability to execute multiple instructions in parallel, to
pipeline instructions, and the use of simple instructions with
rapid execution times yields maximum efficiency and throughput
for PowerPC 750/740 systems.
Power Management
The PowerPC 750/740 microprocessors feature a low-
power 2.6-volt or 1.9-volt design with three power-
saving modes—doze, nap and sleep. These
user-programmable modes progressively reduce the
power drawn by the processor.
These low-power microprocessors offer dynamic
power management to selectively activate functional
units as they are needed by the executing instructions.
Both microprocessors also provide a thermal assist unit
and instruction cache throttling for software-
controllable thermal management.
Cache and MMU Support
The PowerPC 750/740 microprocessors have separate
32-Kbyte, physically-addressed instruction and data
caches. Both caches are eight-way set-associative.
The additional dedicated L2 cache interface with on-
chip L2 tags (shown at right) is provided only by the
MPC750FACT/D
REV. 6
Fact Sheet
M OTOROLA P OWER PC 750 AND
P OWER PC 740 M ICROPROCESSORS
Motorola PowerPC 750
Microprocessor
32b
Address
17b
Address
64b
Data
64b
Data
System Register
Unit
Bus Interface Unit
L2 Control / Tags
System Bus
L2 Cache
Integer
Unit
Integer
Unit
Floating Point
Unit
MMU
Inst. Cache
MPC750 Only
MMU
Data Cache
Load/Store
Unit
Instruction
Unit
Branch Processing
Unit
PowerPC 750/740 Microprocessor
Block Diagram
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