參數(shù)資料
型號: MPC8377E-RDBA
廠商: Freescale Semiconductor
文件頁數(shù): 30/127頁
文件大?。?/td> 0K
描述: BOARD REF DES MPC8377 REV 2.1
設(shè)計資源: MPC8379E-RDB Ref Design Guide
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8377E
所含物品: 板,CD
相關(guān)產(chǎn)品: MPC8378EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
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MPC8378EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8379EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
MPC8379EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8379EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
MPC8379EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8377EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8377EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
125
6
07/2011 In Section 2.2, “Power Sequencing,” updated power down sequencing information.
5
07/2011
In Table 2, “Absolute Maximum Ratings1,” removed footnote 5 from LBIN to OVIN. Also, corrected
footnote 5.
In Table 3, “Recommended Operating Conditions,” added footnote 2 to AVDD.
to –50/50.
tSKRGT_RX and tSKRGT_TX signals.
In Table 33, MII Management AC Timing Specifications,” updated MDC frequency—removed Min and
Max values, added Typical value. Also, updated footnote 2 and removed footnote 3.
In Table 48, PCI DC Electrical Characteristics,” updated VIH min value to 2.0.
In Table 72, TePBGA II Pinout Listing,” added Note to LGPL4/LFRB_B/LGTA_B/LUPWAIT/LPBSE (to
be consistent with AN3665, “MPC837xE Design Checklist.”
In Table 74, Operating Frequencies for TePBGA II,” added Minimum Operating Frequency for eTSEC,
and corrected DDR2 Minimum and Maximum Operating Frequency values.
4
11/2010
In Table 25, RGMII and RTBI DC Electrical Characteristics,” updated VIH min value to 1.7.
to LCRR.
In Table 72, TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and
TEST_SEL1 pins—no change in functionality.
3
03/2010
Mode Only),” added table footnotes .
General Timing Parameters—PLL Bypass Mode,” corrected footnotes for tLBOTOT1, tLBOTOT2, tLBOTOT3.
“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.
heat spreader.
In Section 25.6, “Pull-Up Resistor Requirements,removed “Ethernet Management MDIO pin” from list
of open drain type pins.
In Table 72, TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and
AVDD_P pins.
in Table 72, “TePBGA II Pinout Listing,” added Note 16 to eTSEC pins.
Mode,” updated
csb_clk frequencies available.
In Table 84, Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”
Table 87. Document Revision History (continued)
Revision
Date
Substantive Change(s)
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