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參數(shù)資料
| 型號： | MPC9653FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 159K |
| 代理商： | MPC9653FA |
MPC9653
524
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)
1
1.
AC characteristics apply for parallel output termination of 50
to V
TT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input Reference Frequency
÷ 4 feedback2
PLL Mode, External Feedback
÷ 8 feedback3
Input reference frequency in PLL bypass mode4
2.
÷4 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE =0.
3.
÷8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE =0.
4.
In bypass mode, the MPC9653 divides the input reference clock.
50
25
0
125
62.5
200
MHz
PLL locked
fVCO
VCO Lock Frequency Range5
5.
The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
200
500
MHz
fMAX
Output Frequency
÷ 4 feedback2
÷ 8 feedback3
50
25
125
62.5
MHz
PLL locked
VPP
Peak-to-Peak Input Voltage
PCLK
450
1000
mV
LVPECL
VCMR
6
6.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the
input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Common Mode Range
PCLK
1.2
VCC –0.75
V
LVPECL
tPW,MIN
Input Reference Pulse Width7
7.
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF,MIN.
For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%.
2
ns
t()
Propagation Delay (static phase offset)8
PCLK to FB_IN
8.
Valid for fREF = 50 MHz and FB = ÷ 8 (VCO_SEL = 1). For other reference frequencies: t() [ps] = 50 ps ± (1 ÷ (120 fREF)).
–75
125
ps
PLL locked
tPD
Propagation Delay
PLL and divider bypass (BYPASS = 0), PCLK to Q0–7
PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0–7
1.2
3.0
3.3
7.0
ns
tsk(O)
Output-to-Output Skew9
9.
Refer to APPLICATIONS INFORMATION for part-to-part skew calculation in PLL zero-delay mode.
150
ps
tsk(PP)
Device-to-Device Skew in PLL and Divider Bypass10
10. For a specified temperature and voltage, includes output skew.
1.5
ns
BYPASS =0
DC
Output Duty Cycle
45
50
55
%
PLL locked
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, LZ
Output Enable Time
6.0
ns
tJIT(CC)
Cycle-to-Cycle Jitter
100
ps
tJIT(PER)
Period Jitter
100
ps
tJIT()
I/O Phase Jitter11
RMS (1
σ)
11. I/O phase jitter is reference frequency dependent. Refer to APPLICATIONS INFORMATION for details.
25
ps
BW
PLL Closed Loop Bandwidth12
÷ 4 feedback2
PLL Mode, External Feedback
÷ 8 feedback3
12. –3 dB point of PLL transfer characteristics.
0.8 – 4
0.5 – 1.3
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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