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參數(shù)資料
| 型號(hào)： | MPC9774FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 186K |
| 代理商： | MPC9774FA |
224
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MPC9774
Rev 3, 08/2004
3.3 V 1:14 LVCMOS PLL Clock
Generator
The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With
output frequencies up to 125 MHz and output skews less than 175 ps the device
meets the needs of the most demanding clock applications.
Features
1:14 PLL based low-voltage clock generator
3.3 V power supply
Internal power-on reset
Generates clock signals up to 125 MHz
Maximum output skew of 175 ps
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see APPLICATIONS
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MPC974
52-lead Pb-free Package Available
Functional Description
The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the
VCO frequency range.
The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input relation-
ships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate configurable
feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an
extended PLL input reference frequency range.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alter-
native LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-
figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do
not apply.
The MPC9774 has an internal power-on reset.
The MPC9774 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS
signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines. For series
terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of 1:12.
The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.
MPC9774
FA SUFFIX
52-LEAD LQFP PACKAGE
CASE 848D-03
3.3 V 1:14 LVCMOS
PLL CLOCK GENERATOR
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PDF描述 |
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| MPC9774AE | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC97H73FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9893AE | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| MPC9894VFR2 | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| MPC998FAR2 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9774FAR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC97H73AE | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC97H73AER2 | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC97H73FA | 功能描述:IC PLL CLK GENERATOR 1:12 52LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC97H74AE | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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