參數(shù)資料
型號: 74LCX126MX
廠商: Fairchild Semiconductor
文件頁數(shù): 4/9頁
文件大?。?/td> 0K
描述: IC BUFFER QUAD LV N-INV 14SOIC
標準包裝: 1
系列: 74LCX
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 4
每個元件的位元數(shù): 1
輸出電流高,低: 24mA,24mA
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 14-SOIC
包裝: 標準包裝
其它名稱: 74LCX126MXDKR
BU1572GUW, BU1573KV, BU1574KU
Technical Note
4/12
www.rohm.com
2009.04- Rev.B
2009 ROHM Co., Ltd. All rights reserved.
PIN
No.
PIN
Name
Interface Type *1
In/Out
Active
Level
Init
Description
In/output
type
TYPE 1
TYPE 2
33
MSEL2
MSEL2 *3
MSEL2 *4
In
*
-
Mode select 2
A
34
LCDRS0O/
PWMO1 *5
LCDRS0O/
PWM_O(1)
Out
*
Low
Register select output signal 0/
PWM output for the LCD backlight
E
35
PWMO3 *5/
VLDO
PWM_O(3)
PWM_O(3)/
VLDO
Out
*
Low
PWM output for the LCD backlight/
VLD output signal
E
36
ENAO
-
ENAO
Out
*
Low
RAM write enable output signal
E
37
LCDDO17/
PWMO2 *5
LCDDO17/
PWM_O(2)
LCDDO17/
PWM_O(2)
In/Out
DATA
Low
Data output: bit 17/
PWM output for the LCD backlight
F
38
LCDDO16
In/Out
DATA
Low
Data output:
bit 16
F
39
LCDDO15
In/Out
DATA
Low
Data output:
bit 15
F
40
LCDDO14
In/Out
DATA
Low
Data output:
bit 14
F
41
LCDDO13
In/Out
DATA
Low
Data output:
bit 13
F
42
LCDDO12
In/Out
DATA
Low
Data output:
bit 12
F
43
LCDDO11
In/Out
DATA
Low
Data output:
bit 11
F
44
LCDDO10
In/Out
DATA
Low
Data output:
bit 10
F
45
LCDDO9
In/Out
DATA
Low
Data output:
bit 9
F
46
LCDDO8
In/Out
DATA
Low
Data output:
bit 8
F
47
GND
-
GND
-
Common GROUND
-
48
LCDDO7
In/Out
DATA
Low
Data output:
bit 7
F
49
LCDDO6
In/Out
DATA
Low
Data output:
bit 6
F
50
LCDDO5
In/Out
DATA
Low
Data output:
bit 5
F
51
LCDDO4
In/Out
DATA
Low
Data output:
bit 4
F
52
LCDDO3
In/Out
DATA
Low
Data output:
bit 3
F
53
LCDDO2
In/Out
DATA
Low
Data output:
bit 2
F
54
LCDDO1
In/Out
DATA
Low
Data output:
bit 1
F
55
LCDDO0
In/Out
DATA
Low
Data output:
bit 0
F
56
LCDWRBO/
I2CDEV6B
LCDWRBO
I2CDEV6B *3
In/Out
*
High/
In
Write enable output signal
F
57
LCDCSBO
"H" *6
Out
*
High
Chip select output signal
E
58
SDA /
LCDHSO
-
LCDHSO
Out
*
Low
In/output serial clock/
Horizontal timing output signal
G
59
SDC/
LCDVSO
-
LCDVSO
Out
*
Low
In/output serial clock/
Vertical timing output signal
G
60
RESETB
In
Low
-
System reset signal
B
61
VDDIO
-
PWR
-
DIGITAL IO power source
-
62
DCKO
Out
CLK
Low
Clock output
E
63
GND
-
GND
-
Common GROUND
-
64
VDD
-
PWR
-
CORE power source
-
※Change by setup by the register is possible for the "*" display in the column of an Active level. Moreover, Init is a pin state under reset.
*3 : Please connect with GND
*4 : Please connect with VDDIO
*5 : It selects it according to PWMCNT register (40h).
*6 : “High”output
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