參數(shù)資料
型號(hào): PCA9535D,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 24/26頁(yè)
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24SOIC
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 30
接口: I²C,SM 總線
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SO
包裝: 管件
包括: POR
產(chǎn)品目錄頁(yè)面: 825 (CN2011-ZH PDF)
其它名稱: 568-3377-5
935273945112
PCA9535D
PCA9535_PCA9535C_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 15 September 2008
7 of 31
NXP Semiconductors
PCA9535; PCA9535C
16-bit I2C-bus and SMBus, low power I/O port with interrupt
6.2.2 Registers 0 and 1: Input port registers
This register is an input-only port. It reects the incoming logic levels of the pins,
regardless of whether the pin is dened as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
6.2.3 Registers 2 and 3: Output port registers
This register is an output-only port. It reects the outgoing logic levels of the pins dened
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins dened
as inputs. In turn, reads from this register reect the value that is in the ip-op controlling
the output selection, not the actual pin value.
6.2.4 Registers 4 and 5: Polarity Inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5.
Input port 0 Register
Bit
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
XXXXXXXX
Table 6.
Input port 1 register
Bit
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
XXXXXXXX
Table 7.
Output port 0 register
Bit
7
6
5
4
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
11111111
Table 8.
Output port 1 register
Bit
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
11111111
Table 9.
Polarity Inversion port 0 register
Bit
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
00000000
Table 10.
Polarity Inversion port 1 register
Bit
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
00000000
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