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參數(shù)資料
| 型號： | PEF2080 |
| 廠商： | SIEMENS AG |
| 英文描述： | S/T Bus Interface Circuit(SBC) |
| 中文描述： | S / T的總線接口電路（SBC）的 |
| 文件頁數(shù)： | 39/74頁 |
| 文件大?。?/td> | 2620K |
| 代理商： | PEF2080 |
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Semiconductor Group
40
Operational Description
As an alternative to clock activation via SDI, the asynchronous wake-up pin ENCK (X3 in TE mode)
can be grounded. In this case the timing given in
figure 22
applies. When ENCK is tied to ground
the IOM-clock pulses are delivered by SBC at all times.
Figure 22
Activation of the IOM
Interface via ENCK (pin X3) in TE Mode (NB: DCL out of scale)
The clock pulses will be enabled again when the SBC recognizes a low level on SDI (command
Timing TIM = “0000”) or when a non-zero level on the S line interface is detected. The clocks are
turned on after approximately 0.5 to 4 ms (dependent on the capacitances on XTAL 1/2).
After the clocks have been enabled this is indicated by the PU code in the C/l channel. The
downstream unit may then insert a valid code in the C/l channel. The continuous supply of timing
signals by the SBC is ensured as long as there is no DIU command in the C/l channel. If timing
signals are no longer required and activation is not yet requested, the downstream unit may indicate
this by sending DIU.
At power up, a reset pulse (RST) should be applied to bring the SBC to a well defined state. This
state is G1 for NT or LT-S mode, and F3 for TE or LT-T mode. The oscillator and energy intensive
analog components are disabled and the S-line awake detector is active after the pulse. All outputs
are in high impedance state during the hardware reset pulse. In TE mode when ENCK is grounded,
however, the SBC will still supply IOM timing during a reset pulse, and the message “Error
Indication” EI is present in the C/l channel. Similarly, in NT mode, activation of pin CP brings the
outputs to low impedance during a reset pulse and the message EI is sent in the C/l channel.
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