參數(shù)資料
型號(hào)： PF38F40L0YUQ0
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, PBGA88
封裝： 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件頁數(shù)： 43/99頁
文件大小： 1419K
代理商： PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
48
Order Number: 313295-002US
NOTE:
The waveform above illustrates the Latency Count of 4 with Flow-through feature. The Flow-through
feature will be shown only when the initial access time is one clock less than the LC setting.
10.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of
WAIT. When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is
asserted-low. WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted and RST# deasserted).
10.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(CR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous single word read mode, WAIT is set to an
“de-asserted” state as determined by CR[10]. See Table 18, “WAIT Summary Table” on
Figure 17. Example Latency Count Setting with Flow- through feature
A
MAX-16
CLK
CE#
ADV#
R2
Valid
Output
Valid
Output
High Z
t
ADD
t
DATA
2nd
1st
3rd
4th
5th
Code 4
A/DQ
15-0
Valid Address
6th
t
CHQV
Table 18. WAIT Summary Table
CONDITION
WAIT
CE# = VIH
CE# = VIL
High-Z
Driven
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