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參數(shù)資料
| 型號： | PF38F40L0YUQ0 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件頁數(shù)： | 47/99頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
51
Intel StrataFlash Wireless Memory (L18)
When performing synchronous burst reads with BW set (no wrap), an output delay may
occur when the burst sequence crosses its first device-row (16-word) boundary. If the
burst sequence’s start address is 4-word aligned, then no delay occurs. If the start
address is at the end of a 4-word boundary, the worst case output delay is one clock
cycle less than the first access Latency Count. This delay can take place only once, and
doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT
informs the system of this delay when it occurs.
10.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 19, “Burst Sequence Word Ordering” on page 50). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
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