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參數(shù)資料
| 型號(hào)： | PPG312F-20M |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 標(biāo)準(zhǔn)邏輯 |
| 英文描述： | SPECIALTY LOGIC CIRCUIT, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 46K |
| 代理商： | PPG312F-20M |
PPG312F
Doc #97008
DATA DELAY DEVICES, INC.
2
1/15/97
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
APPLICATION NOTES
DEVICE TIMING
The timing definitions and restrictions for the
PPG312F are shown in Figure 1. The unit is
activated by a rising edge on the TRIG input.
After a time, TTO (called the inherent delay), the
rising edge of the pulse appears at OUT. The
duration of the pulse is given by the above
equation. For the duration of the pulse, the
device ignores subsequent triggers. Once the
falling edge of the pulse has appeared at OUT,
an additional time, TOTR, is required before the
device can respond to the next trigger.
At power-up, the state of the PPG312F is
unknown. Consequently, after power is applied,
the unit may not respond to input triggers for a
time equal to the maximum pulse width, PWT.
After this time, the unit will function properly. If
your application requires that the device function
immediately, issue a quick reset at power-up.
POWER SUPPLY BYPASSING
The PPG312F relies on a stable power supply to
produce repeatable pulses within the stated
tolerances. A 0.1uf capacitor from VCC to GND,
located as close as possible to each VCC pin, is
recommended. A wide VCC trace should
connect all VCC pins externally, and a clean
ground plane should be used.
INCREMENT TOLERANCES
Please note that the increment tolerances listed
represent a design goal. Although most
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
`
TOAX
TRTS
TTW
TTO
PWA
A11-A0
RES
TRIG
OUT
OUT/
Figure 1: Timing Diagram
A i
Ai+1
TSKEW
TATS
TRO
TOTR
TTW
TRW
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