參數(shù)資料
型號: PSD9332V20JT
廠商: 意法半導(dǎo)體
英文描述: High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 45/110頁
文件大小: 1737K
代理商: PSD9332V20JT
45/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
PSD Interface to a Non-Multiplexed 8-Bit Bus
Figure
20
shows an example of a system using a
MCU with an 8-bit non-multiplexed bus and a
PSD. The address bus is connected to the ADIO
Port, and the data bus is connected to Port A. Port
A is in tri-state mode when the PSD is not access-
ed by the MCU. Should the system address bus
exceed sixteen bits, Ports B, C, or D may be used
for additional address inputs.
Data Byte Enable Reference
MCUs have different data byte orientations. Table
17
shows how the PSD interprets byte/word oper-
ations in different bus WRITE configurations.
Even-byte refers to locations with address A0
equal to '0' and odd byte as locations with A0 equal
to ’1.’
MCU Bus Interface Examples
Figure
21
through
25
show examples of the basic
connections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PS-
Dsoft Express Configuration.
Table 17. Eight-Bit Data Bus
Figure 20. An Example of a Typical 8-bit Non-Multiplexed Bus Interface
BHE
A0
D7-D0
X
0
Even Byte
X
1
Odd Byte
MCU
WR
RD
BHE
ALE
RESET
D[7:0]
A[15:0]
A[23:16]
D[7:0]
ADIO
PORT
PORT
A
PORT
B
PORT
C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
PSD
AI02879C
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